1. Field of the Invention
The present invention relates to a semiconductor device, a test system and a method of testing on die termination (ODT) circuit.
2. Description of the Related Art
Recently, swing margin of transmitted signals between semiconductor devices has been gradually reduced in order to increase transmission speed of a signal. As the swing margin is reduced, the semiconductor devices are more affected by external noise and the signal reflection increases. The signal reflection is caused by impedance mismatching between the semiconductor devices.
When impedance mismatching between the semiconductor devices occurs, it becomes difficult to transmit signals at a high speed and there is a greater chance to have a transmission error due to distortion of data outputted from the semiconductor devices.
Therefore, a termination circuit is included in electronic devices for impedance matching between the semiconductor devices. The termination circuit may also reduce reflected waves that are generated during signal transmission.
For the purposes described above, semiconductor devices, and more particularly, semiconductor memory devices, that include on die termination (ODT) circuits coupled to pads have been developed.
FIG. 1 is a circuit diagram illustrating a conventional ODT circuit included in semiconductor devices. The conventional ODT circuit shown in FIG. 1 is disclosed in Korean Patent Laid-Open Publication No. 2003-0096064.
Referring to FIG. 1, the ODT circuit includes a positive channel metal oxide semiconductor (PMOS) transistor MP1, a negative channel metal oxide semiconductor (NMOS) transistor MN1, an inverter 2, resistors R1 and R2, and a pad 4. The resistors R1, R2 are termination resistors for impedance matching. When an ODT control signal ODT_EN is logic ‘low’, the PMOS transistor MP1 and the NMOS transistor MN1 are both off and thus the ODT is not enabled. When the ODT control signal ODT_EN is logic ‘high’, both of the PMOS transistor MP1 and the NMOS transistor MN1 are turned on and a signal applied to the pad 4 is terminated with a voltage divided by resistors R1 and R2.
A termination voltage has a voltage level between power supply voltage VDDQ and ground voltage. When the resistor R1 and the resistor R2 have the same resistance and the transistors MP1 and MP2 have on-resistance identical to each other, the termination voltage corresponds to ½ power supply voltage VDDQ. That is, the ODT circuit in FIG. 1 may provide a desired termination resistance with the two resistors R1 and R2.
The PMOS transistor MP1 and the NMOS transistor MN1 typically have a large size so as to reduce on-resistance. The ODT control signal ODT_EN of logic ‘high’ is applied so that the signal is terminated with a predetermined level of voltage. On the contrary, when there is no need to terminate a signal applied through the pad 4, the ODT control signal ODT_EN of logic ‘low’ is applied so as to disable the ODT circuit.
For impedance matching between semiconductor devices, an ODT circuit is included in semiconductor devices. The ODT circuit needs to be tested in advance to confirm whether the ODT circuit functions correctly. However, the ODT circuit includes tens or more of pins. It is not an easy task to examine each of the pins coupled to the ODT circuit. Furthermore, when hundreds of semiconductor memory devices are tested at the same time, the number of pins that are simultaneously examined is considerable, thereby decreasing accuracy of the test.
Therefore, for an accurate test result, it is desirable to reduce the number of pins that are used for an ODT test.